I²C Pull-Up Resistor

Optimal pull-up resistor for I²C bus speed and capacitance.

// I²C is open-drain — the pull-ups have to charge the bus fast enough without overloading the sink

Recommended pull-up
1.8 kΩ

valid range 967 Ω – 3.54 kΩ · one on SDA, one on SCL

Minimum Rp
967 Ω
sink limit 3 mA
Maximum Rp
3.54 kΩ
rise time 300 ns
Ideal (log centre)
1.85 kΩ
√(Rmin × Rmax)

// check a specific value

Rise time
153 ns
limit 300 ns
Sink current
1.61 mA
limit 3 mA
Current per line when low
1.83 mA
× 2 lines
IN SPEC1.8 kΩ rises in 153 ns and sinks 1.61 mA — both inside the limits.

// estimating bus capacitance

▸ show formulas
The floor comes from the sink current the bus drivers guarantee:
Rp_min = (Vdd − Vol) / Iol
Vol = 0.4 V, Iol = 3 mA (20 mA in Fast-mode Plus)

The ceiling comes from the rise-time budget:
Rp_max = t_rise / (0.8473 × Cb)
0.8473 = ln(7/3), the RC time from 0.3 Vdd to 0.7 Vdd
t_rise = 1000 ns / 300 ns / 120 ns for 100 k / 400 k / 1 M

The spec caps total bus capacitance at 400 pF. 4.7 kΩ is the usual default at 3.3 V and 100 kHz; drop to 2.2 kΩ or 1 kΩ for fast mode or a long bus. Fit exactly one pair of pull-ups per bus — modules with their own pull-ups stack in parallel and quietly halve the resistance each time.
I2Cpull-upSDASCLbusmicrocontroller

About this calculator

I²C lines are open-drain: devices can pull them low but never drive them high. Getting back to a logic high is the pull-up resistor's job, and its value is a compromise between two hard limits that close in from either side.

This calculator finds both limits for your bus and recommends a value between them. It also lets you check a specific resistor against the rise time and sink current the specification allows.

How it works

The lower limit comes from current. When a device pulls the line low it has to sink whatever the pull-up passes, and the specification only guarantees 3 mA (20 mA in Fast-mode Plus) while still holding the line below 0.4 V. That gives Rp_min = (Vdd − 0.4) / Iol.

The upper limit comes from speed. Releasing the line lets the bus capacitance charge through the pull-up — an RC curve, not an edge. The specification budgets 1000 ns for the rise at 100 kHz, 300 ns at 400 kHz and 120 ns at 1 MHz, measured from 0.3 to 0.7 Vdd. That interval is ln(7/3) = 0.8473 time constants, giving Rp_max = t_rise / (0.8473 × Cb).

Anywhere between those two works. The calculator suggests the geometric mean, which sits centrally on a logarithmic scale — the right kind of centre when resistor values themselves are spaced logarithmically.

Bus capacitance is the variable that squeezes the window. Every device pin contributes roughly 10 pF and every centimetre of trace or wire about 1 pF. The specification caps the total at 400 pF, and long ribbon cables blow through that quickly.

Rp_min = (Vdd − Vol) / Iol Vol = 0.4 V, Iol = 3 mA
Rp_max = t_rise / (0.8473 × Cb)
0.8473 = ln(7/3) 0.3 Vdd to 0.7 Vdd
Rp_ideal = √(Rp_min × Rp_max)
I_sink = (Vdd − 0.4) / Rp

Worked example

Three sensors on a short 3.3 V bus running at 400 kHz, with roughly 100 pF of total capacitance.

  1. Rp_min = (3.3 − 0.4) / 0.003 = 967 Ω
  2. Rp_max = 300e-9 / (0.8473 × 100e-12) = 3541 Ω
  3. Geometric mean: √(967 × 3541) = 1850 Ω
  4. Nearest E24 value: 1.8 kΩ
  5. Rise time with 1.8 kΩ: 0.8473 × 1800 × 100e-12 = 153 ns — inside the 300 ns budget
  6. Sink current: 2.9 / 1800 = 1.6 mA — well under the 3 mA limit

1.8 kΩ on each of SDA and SCL. The often-quoted 4.7 kΩ would give a 398 ns rise time here — out of spec for 400 kHz, though it would work fine at 100 kHz.

Practical notes

  • One pair of pull-ups per bus, not per device. Breakout boards frequently include their own, and three modules with 4.7 kΩ each gives you 1.6 kΩ — sometimes fine, sometimes too strong. Check the boards and remove the extras.
  • 4.7 kΩ is the sensible default at 3.3 V and 100 kHz. Drop to 2.2 kΩ or 1 kΩ for 400 kHz, a long bus, or many devices.
  • If the bus will not work at speed, look at the rising edge on a scope. A rounded, exponential-looking rise means the pull-up is too weak for the capacitance.
  • Mixing 3.3 V and 5 V devices is common but needs care. Pulling up to 3.3 V often works if the 5 V parts accept 3.3 V as a logic high; otherwise use a proper level-shifter with the pull-ups on both sides.
  • The pull-ups draw current continuously whenever the bus is low. On a battery-powered design, weaker pull-ups and a slower clock cut that meaningfully.
  • Past 400 pF of bus capacitance, no resistor value satisfies both limits. That is the point for an active buffer such as the P82B96 or PCA9615.

Frequently asked questions

What value pull-up resistor should I use for I²C?

4.7 kΩ is the standard default for 3.3 V at 100 kHz. For 400 kHz or a longer bus, 2.2 kΩ or 1.8 kΩ. The right answer depends on your bus capacitance, which is what the calculator works from.

Do I need pull-ups on both SDA and SCL?

Yes. Both are open-drain and both need to get back to a logic high. Use the same value on each.

Why does my I²C bus fail at higher speed but work at 100 kHz?

Almost always rise time. The rise-time budget shrinks from 1000 ns to 300 ns going from 100 kHz to 400 kHz, so a pull-up that was comfortable becomes too weak. Fit smaller resistors or shorten the bus.

What happens if the pull-up is too strong?

The device pulling the line low cannot sink enough current to get below 0.4 V, so the receiver may not register a valid low. Edges get faster but levels become unreliable, and the driver runs hot.

How much capacitance does my bus have?

Roughly 10 pF per device pin plus about 1 pF per centimetre of trace or wire. Four devices on a 15 cm bus is around 55 pF. The specification limits the total to 400 pF.

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