Reference

Quick-reference tables and charts for common electronics work.

E24 Standard Resistor Values

// 24 values per decade · multiply by 1 Ω, 10 Ω, 100 Ω, 1 kΩ, 10 kΩ, 100 kΩ, or 1 MΩ

1.0
1.1
1.2
1.3
1.5
1.6
1.8
2.0
2.2
2.4
2.7
3.0
3.3
3.6
3.9
4.3
4.7
5.1
5.6
6.2
6.8
7.5
8.2
9.1

Ceramic Capacitor Codes

// 3-digit code: first 2 digits × 10^(3rd digit) pF · e.g. 104 = 10 × 10⁴ pF = 100 nF

CodeValue CodeValue
100 10 pF 15015 pF
220 22 pF 33033 pF
470 47 pF 68068 pF
101 100 pF 151150 pF
221 220 pF 471470 pF
681 680 pF 1021 nF
222 2.2 nF 3323.3 nF
472 4.7 nF 6826.8 nF
103 10 nF 22322 nF
473 47 nF 68368 nF
104 100 nF (0.1 µF) 224220 nF
474 470 nF 1051 µF

AWG Wire Gauge Chart

// copper wire · resistance at 20 °C · current rating for chassis wiring in free air (NEC)

AWG Diameter (mm) Ω / m Max current (A)
30 0.255 0.339 0.5
28 0.321 0.213 0.8
26 0.405 0.134 1.0
24 0.511 0.0842 2.0
22 0.644 0.0530 3.0
20 0.812 0.0333 5.0
18 1.024 0.0209 7.0
16 1.291 0.0132 13
14 1.628 0.00829 17
12 2.053 0.00521 20
10 2.588 0.00328 30

Logic Level Reference

// VIH = min input HIGH · VIL = max input LOW · VOH = min output HIGH · VOL = max output LOW

Family VCC VIH min VIL max VOH min VOL max
74LS TTL 5V 2.0V 0.8V 2.4V 0.5V
74HC CMOS 5V 3.5V 1.0V 4.4V 0.1V
3.3V LVTTL 3.3V 2.0V 0.8V 2.4V 0.4V
3.3V LVCMOS 3.3V 2.0V 0.8V 2.4V 0.4V

Compatibility quick-check

✓  3.3 V → 5 V TTL — works. VOH (2.4 V) ≥ VIH (2.0 V). ⚠  3.3 V → 5 V CMOS — may fail. VOH (2.4 V) < VIH (3.5 V). Use a level shifter or a 74HCT part. ✕  5 V → 3.3 V input — use a level shifter unless the input is explicitly 5 V-tolerant.

Common IC Pinouts

// pin 1 marked by dot or notch on physical package

NE555 / LM555

DIP-8 · SOIC-8

General-purpose timer. Astable (oscillator) or monostable (one-shot) modes.

1 GND Ground
2 TRIG Trigger — output HIGH when < ⅓ VCC
3 OUT Output, source/sink up to 200 mA
4 RST Reset, active LOW — tie HIGH if unused
5 CV Control voltage (⅔ VCC ref) — bypass with 10 nF if unused
6 THR Threshold — resets output LOW when > ⅔ VCC
7 DIS Discharge — open-collector, connects to timing cap
8 VCC Supply 4.5 V – 16 V

LM7805

TO-220 · TO-92 · D2PAK

Fixed +5 V linear regulator. Same pinout applies to LM7812, LM7815, etc.

1 IN Unregulated input (+7 V – +35 V)
2 GND Ground
3 OUT Regulated +5 V output, up to 1 A

LM317

TO-220 · TO-92 · D2PAK

Adjustable regulator. Vout = 1.25 × (1 + R2/R1). Min load 10 mA recommended.

1 ADJ Adjust — sets Vout via R1/R2 resistor divider to GND
2 OUT Output (1.25 V – 37 V, up to 1.5 A)
3 IN Unregulated input (must exceed Vout + 3 V dropout)

LM741

DIP-8 · SOIC-8

Classic single op-amp. Requires dual supply. Modern designs prefer LM358 or TL071.

1 NULL A Offset null — connect 10 kΩ pot wiper between pins 1 & 5
2 IN − Inverting input
3 IN + Non-inverting input
4 V − Negative supply
5 NULL B Offset null — see pin 1
6 OUT Output
7 V + Positive supply
8 N/C No connect

LM358

DIP-8 · SOIC-8

Dual op-amp, single or dual supply (3 V – 32 V). Rail-to-rail output.

1 OUT1 Output, amplifier 1
2 IN1 − Inverting input 1
3 IN1 + Non-inverting input 1
4 GND Ground (negative supply for split-rail use)
5 IN2 + Non-inverting input 2
6 IN2 − Inverting input 2
7 OUT2 Output, amplifier 2
8 VCC Supply

LM386

DIP-8

Audio power amplifier, 4 V – 12 V. Default gain 20×; 200× with 10 µF between pins 1 & 8.

1 GAIN Gain — leave open (20×) or add 1.2 kΩ + 10 µF to pin 8 for 200×
2 IN − Inverting input — bypass to GND with 10 µF for single-ended use
3 IN + Non-inverting input — audio signal here
4 GND Ground
5 OUT Output — couple to speaker via 250 µF cap
6 VS Supply (4 V – 12 V)
7 BYPASS Bypass — add 10 µF cap to GND for stability
8 GAIN Gain — see pin 1

74HC595

DIP-16 · SOIC-16

8-bit serial-in / parallel-out shift register with output latch. Daisy-chainable.

1 QB Parallel output B
2 QC Parallel output C
3 QD Parallel output D
4 QE Parallel output E
5 QF Parallel output F
6 QG Parallel output G
7 QH Parallel output H
8 GND Ground
9 QH' Serial output — connect to SER of next 595 to chain
10 SRCLR Shift register clear, active LOW — tie HIGH if unused
11 SRCLK Shift register clock — data clocked in on rising edge
12 RCLK Latch clock — transfers shift register to output pins
13 OE Output enable, active LOW — tie LOW to enable outputs
14 SER Serial data input
15 QA Parallel output A (first bit shifted in)
16 VCC Supply 2 V – 6 V

CD4017

DIP-16 · SOIC-16

Johnson decade counter. One output goes HIGH per clock pulse; resets after Q9.

1 Q5 Output 5
2 Q1 Output 1
3 Q0 Output 0 — HIGH after reset
4 Q2 Output 2
5 Q6 Output 6
6 Q7 Output 7
7 Q3 Output 3
8 VSS Ground
9 Q8 Output 8
10 Q4 Output 4
11 Q9 Output 9
12 CARRY Carry out — HIGH for counts 0–4, LOW for 5–9
13 CLKE Clock enable, active LOW — tie LOW to enable
14 CLK Clock — advances count on rising edge
15 RST Reset, active HIGH — tie LOW if unused
16 VDD Supply 3 V – 15 V

L293D

DIP-16 · SOIC-16

Dual H-bridge, 600 mA per channel (1.2 A peak), up to 36 V motor supply. Built-in flyback diodes.

1 EN1 Enable channels 1 & 2, active HIGH
2 1A Input 1
3 1Y Output 1 — motor terminal A
4 GND Ground
5 GND Ground
6 2Y Output 2 — motor terminal B
7 2A Input 2
8 VS Motor supply, up to 36 V
9 EN2 Enable channels 3 & 4, active HIGH
10 3A Input 3
11 3Y Output 3 — motor 2 terminal A
12 GND Ground
13 GND Ground
14 4Y Output 4 — motor 2 terminal B
15 4A Input 4
16 VSS Logic supply (5 V)

ATmega328P

DIP-28 (Arduino Uno)

Shown with Arduino Uno pin mapping. XTAL pins used by on-chip oscillator on standalone boards.

1 RESET Reset, active LOW — 10 kΩ pull-up to VCC
2 PD0 D0 / RXD
3 PD1 D1 / TXD
4 PD2 D2 / INT0
5 PD3 D3 / INT1 / PWM
6 PD4 D4
7 VCC Digital supply — 100 nF bypass cap to GND
8 GND Ground
9 PB6 XTAL1 — crystal or external clock in
10 PB7 XTAL2 — crystal out
11 PD5 D5 / PWM
12 PD6 D6 / PWM
13 PD7 D7
14 PB0 D8
15 PB1 D9 / PWM
16 PB2 D10 / PWM / SS
17 PB3 D11 / PWM / MOSI
18 PB4 D12 / MISO
19 PB5 D13 / SCK / onboard LED
20 AVCC ADC supply — connect to VCC via 10 µH + 100 nF to GND
21 AREF ADC voltage reference — bypass with 100 nF to GND
22 GND Ground
23 PC0 A0
24 PC1 A1
25 PC2 A2
26 PC3 A3
27 PC4 A4 / SDA
28 PC5 A5 / SCL